1. Field of the Invention
The present invention relates to a negative resist composition, especially a negative resist composition using a polymer suitable as a base resin of a chemically amplified negative resist composition, and also to a patterning process.
2. Description of the Related Art
As the LSI advances toward a higher integration and a faster processing speed, miniaturization of a pattern rule is progressing rapidly. Especially expansion of a flash memory market and increase in a memory capacity are towing miniaturization thereof. The 20-nm node device is mass-produced by the double patterning using the ArF lithography as the most advanced miniaturization technology (Non-Patent Document 1).
However, the EUV exposure technology, which is receiving a high expectation as the next generation exposure technology, has a low throughput due to the low output power of a laser beam, so that application thereof to the mass production has not been realized yet. The multi-beam EB has a problem that controllability of each beam is not clear yet, so that an investigation is being carried out on the quadruple patterning in which the double patterning with the ArF exposure is repeated twice: however, this becomes an extremely expensive process. As mentioned above, miniaturization of the pattern rule appears to be approaching to its end from the viewpoints of the technology and the economy.
On the other hand, an investigation is being carried out to enhance the integration degree by stacking the transistors vertically. In the flash memory, a device having a configuration of the laminated films through which the vertical gate is pierced is being investigated. In this case, the integration degree is determined by the number of the laminated films; and thus, enhancement of the integration degree can be achieved without depending on the miniaturization. Development of the miniaturization has been carried out with the aim not only to seek high performances including the increase in the processing speed of the device but also rather to improve the productivity and to cut the cost by increasing the number of the chips that can be obtained from one wafer. In the method to enhance the integration degree by increasing the number of the laminated films as mentioned above, the cost becomes higher as the integration degree is made higher; and thus, in the economic view point this method is different from the way with which the integration degree is enhanced by promoting the miniaturization. Moreover, in this method, there are technical problems in the way to form the myriad laminated films without a defect as well as in the way to form the vertical gate with a high precision. Accordingly, there exist technical and economic difficulties in the vertical transistor as well.
Besides, the 3D-IC in which the memory and the logic are mounted together on one chip is being investigated. By this 3D-IC technology, one chip mounted with multiple functions can be formed. In the movement from a smartphone, which is a main stream today, to a wearable information terminal, development of an extremely small-sized multifunctional chip is assumed to be essential.
As the method to form the 3D-IC, a method to connect the memory with the logic by a bump or a silicon interposer is generally used. In this method, however, the memory and the logic are arranged side by side, so that this does not bring about significant reduction in the chip size. On the other hand, the method in which the logic and the memory are laminated and connected by means of a through electrode (TSV: through-silicon via) whereby communicating between them can bring about significant reduction in the chip size.
For patterning the silicon interposer and the TSV, a thick resist film is used. This thick resist film remains as an insulation film after patterning, so that this is required to have a high durability.